View MAX5195_289438.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2557; Rev 0; 7/02
14-Bit, 260Msps High-Dynamic Performance DAC
General Description
The MAX5195 is an advanced, 14-bit, 260Msps digitalto-analog converter (DAC) designed to meet the demanding performance requirements of signal synthesis applications found in wireless base stations and other communication systems. Operating from a single 5V supply, this DAC offers exceptional dynamic performance such as 77dBc spurious-free dynamic range (SFDR) at fOUT = 19.4MHz, while supporting update rates beyond 260Msps. The MAX5195 current-source array architecture supports a full-scale current range of 10mA to 20mA, which allows a differential output voltage swing between 0.5VP-P and 1VP-P. The MAX5195 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low-noise performance. Additionally, a separate reference input pin allows the user to apply an external reference source for optimum flexibility. The digital and clock inputs of the MAX5195 are designed for differential LVPECL-compatible voltage levels. The MAX5195 is available in a 48-lead QFN package with exposed paddle and is specified for the extended industrial temperature range (-40C to +85C). o 260Msps Output Update Rate o Excellent SFDR Performance To Nyquist (-12dBFS) At 19.4MHz Output = 77dBc At 51.6MHz Output = 76dBc o Industry-Leading IMD Performance For 4 Tones (-15dBFS) At 18MHz Output = 86dBc At 31MHz Output = 84dBc o Low Noise Performance SNR = 160dB/Hz at fOUT = 19.4MHz o On-Chip 1.2V Bandgap Reference o 20mA Full-Scale Current o Single 5V Supply o Differential LVPECL-Compatible Digital Inputs o 48-Lead QFN-EP Package
Features
MAX5195
Ordering Information
PART MAX5195EGM TEMP RANGE -40C to +85C PIN-PACKAGE 48 QFN-EP*
Applications
Base Stations: Single-/Multi-Carrier UMTS, GSM
*EP = Exposed paddle.
Pin Configuration
DVCC DGND D10P D10N D11P D11N D12P D12N D13P D13N
39 38
Direct IF Synthesis Digital-Signal Synthesis Broadband Cable Systems Automated Test Equipment Instrumentation
D9P D8N D8P D7N D7P CLKP CLKN D6N D6P D5N D5P D4N
1 2 3 4 5 6 7 8 9 10 11 12
48
D9N
TOP VIEW
47
46
45
44
43
42
41
40
37 36 35 34 33 32 31 30 29 28 27 26 25
REFIN
LMDS, MMDS, Point-to-Point Microwave
RSET AVCC AMPOUT AVCC AVCC OUTP OUTN AVCC AGND AGND REFOUT AVCC
MAX5195
13
14
15
16
17
18
19
20
21
22
23
________________________________________________________________ Maxim Integrated Products
DVCC DGND D2N D2P
QFN
D1N D1P D0N D0P T.P.
D4P
D3N D3P
24
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC to AGND..............................................-0.3V to +6V AVCC, DVCC to DGND..............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V D0N-D013, D0P-D13P, T.P. to DGND .................-0.3V to +3.6V OUTP, OUTN, AMPOUT, REFOUT, CLKP, CLKN, RSET to AGND..........................................-0.3V to +6V REFIN Voltage Range...............................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 48-Pin QFN-EP (thermal resistance JA = +37C/W)....2162W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = DVCC = 5V, AGND = DGND = 0, external reference VREFIN = 1.196V, RT = 27.4 referenced to AVCC, VOUT = 1VP-P, RSET = 3.83k, fCLK = 156MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full-Scale Gain Error (Note 2) DYNAMIC PERFORMANCE Maximum Throughput Rate Signal-to-Noise Ratio fCLK SNR Full-scale output, within Nyquist window, fCLK = 260MHz, fOUT = 19.4MHz fOUT = 1MHz, -2dBFS Spurious-Free Dynamic Range to Nyquist, -12dBFS fCLK = 156MHz SFDR fCLK = 260MHz fCLK = 156MHz SFDR fCLK = 260MHz fOUT = 19.42MHz fOUT = 51.67MHz fOUT = 19.4MHz fOUT = 51.61MHz fOUT = 19.42MHz fOUT = 51.67MHz fOUT = 19.42MHz fOUT = 51.61MHz fOUT = 1.27MHz fOUT = 9.53MHz 2nd-Order Harmonic Distortion, -12dBFS HD2 fCLK = 156MHz fOUT = 19.42MHz fOUT = 28.82MHz fOUT = 38.42MHz fOUT = 51.67MHz fCLK = 260MHz fOUT = 70.05MHz 260 160 89 77 76 74 72 82 75 82 76 -88 -86 -82 -79 -77 -79 -72 dBc dBc dBc MHz dB/Hz INL DNL VOS GE Best-straight-line fit TA = +25C (Note 1) Internal reference External reference -3.3 14 2 1.5 0.05 2.5 1.6 +3.0 0.1 6 4 LSB LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
Spurious-Free Dynamic Range 10MHz Window, -12dBFS
2
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = DVCC = 5V, AGND = DGND = 0, external reference VREFIN = 1.196V, RT = 27.4 referenced to AVCC, VOUT = 1VP-P, RSET = 3.83k, fCLK = 156MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS fOUT = 1.27MHz fOUT = 9.53MHz 3rd-Order Harmonic Distortion, -12dBFS HD3 fCLK = 156MHz fOUT = 19.42MHz fOUT = 28.82MHz fOUT = 38.42MHz fOUT = 51.64MHz fCLK = 260MHz 2-Tone IMD, -9dBFS, 200kHz Frequency Spacing fCLK = 156MHz IM3 fCLK = 260MHz fCLK = 156MHz IM3 fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz fOUT = 70.05MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz fOUT = 18MHz fOUT = 31MHz 1.136 MIN TYP -90 -85 -81 -78 -78 -79 -80 92 90 91 89 89 87 88 87 86 84 86 84 81 79 81 78 80 77 79 76 75 73 76 74 1.196 1.196 8% 30 200 1.5 1 1.255 V V V/C A mA M dBc dBc dBc dBc dBc dBc dBc MAX UNITS
MAX5195
2-Tone IMD, -12dBFS, 200kHz Frequency Spacing
4-Tone Power Ratio, -15dBFS, 200kHz Frequency Spacing
4-Tone Power Ratio, -18dBFS, 200kHz Frequency Spacing
8-Tone Power Ratio, -21dBFS, 200kHz Frequency Spacing
8-Tone Power Ratio, -24dBFS, 200kHz Frequency Spacing
REFERENCE AND CONTROL AMPLIFIER Internal Reference Voltage Range Reference Input Voltage Range Internal Reference Voltage Drift Internal Reference Sink/Source Current Amplifier Input Impedance VREFOUT VREFIN TCOREF ISINK ISOURCE RIN
_______________________________________________________________________________________
3
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = DVCC = 5V, AGND = DGND = 0, external reference VREFIN = 1.196V, RT = 27.4 referenced to AVCC, VOUT = 1VP-P, RSET = 3.83k, fCLK = 156MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER ANALOG OUTPUT TIMING Output Fall Time Output Rise Time Glitch Energy TIMING CHARACTERISTICS Data-to-Clock Setup Time (D0N-D13N, D0P-D13P) Data-to-Clock Hold Time (D0N-D13N, D0P-D13P) Propagation Delay Time Minimum Clock Pulse Width High Minimum Clock Pulse Width Low Input Logic High Input Logic Low Input Logic Current, Logic High Input Logic Current, Logic Low Digital Input Capacitance POWER SUPPLIES Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Current Digital Supply Current Power Dissipation Power-Supply Rejection Ratio AVCC DVCC IAVCC IDVCC PDISS PSRR AVCC = DVCC = 5V AVCC = DVCC = 5V AVCC = DVCC = 5V AVCC = DVCC = 5V 5% (Note 4) 4.75 4.75 5 5 48 190 1190 0.2 5.25 5.25 58 230 1440 V V mA mA mW %FS/V tSETUP tHOLD tPD tCH tCL VIH VIL IIH IIL CIN VIH = 2.4V VIL = 1.6V -300 -300 50 10 2 Referenced to the rising edge, Figure 4 Referenced to the rising edge, Figure 4 (Note 3) CLKP, CLKN CLKP, CLKN 1.6 1.6 2.4 1.6 +300 +300 0.5 0.5 0.5 1 1.1 ns ns ns ns ns V V A A pF tFALL tRISE 90% to 10% 10% to 90% 0.8 0.8 0.5 ns ns pV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (D0N-D13N, D0P-D13P, CLKP, CLKN)
Note 1: Offset error is the deviation of the output voltage from its ideal value at midscale. Note 2: Full-scale gain error is the deviation of the output voltage from the ideal full-scale value. The actual full-scale voltage is determined by VOUTP - VOUTN, when D0P-D13P are set high and D0N-D13N are set low. Note 3: Propagation delay is the time difference between the active edge of the clock and the active edge of the output. Note 4: Power-supply rejection ratio is the full-scale output change as the supply voltage varies over its specified range.
4
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC
Typical Operating Characteristics
(AVCC = DVCC = 5V, external reference VREFIN = 1.196V, fCLK = 156.072MHz, RT = 27.4 referenced to AVCC, CL = 15pF, VOUT = 1VP-P, RSET = 3.83k, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY
MAX5195 toc01
MAX5195
DIFFERENTIAL NONLINEARITY
MAX5195 toc02
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5195 toc03
2.0 1.5 1.0
3 2 1 0 -1
1.20
1.19 VREFOUT (V) 0 2048 4096 6144 8192 10240122881433616384 DIGITAL INPUT CODE DNL (LSB)
INL (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 DIGITAL INPUT CODE
1.18
1.17 -2 -3 1.16 -40 -15 10 35 60 85 TEMPERATURE (C)
REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX5195 toc04
OFFSET ERROR vs. TEMPERATURE
MAX5195 toc05
GAIN ERROR vs. TEMPERATURE
MAX5195 toc06
1.1904
0
1.75
1.1900 VREFOUT (V)
-0.02 OFFSET ERROR (%FS)
1.70 GAIN ERROR (%FS)
1.1896
-0.04
1.65
1.1892
-0.06
1.60
1.1888
-0.08
1.55
1.1884 4.750
-0.10 4.875 5.000 5.125 5.250 -40 -15 10 35 60 85 ANALOG SUPPLY VOLTAGE (V) TEMPERATURE (C)
1.50 -40 -15 10 35 60 85 TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
MAX5195 toc07
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5195 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 156.072MHz)
MAX5195 toc09
250
250
100 90 80 -6dBFS -12dBFS
200 IAVCC, IDVCC (mA)
200 IAVCC, IDVCC (mA)
150
DIGITAL SUPPLY CURRENT
150
DIGITAL SUPPLY CURRENT
SFDR (dBc)
70 -18dBFS 60 50 40
100
ANALOG SUPPLY CURRENT
100
ANALOG SUPPLY CURRENT
50
50
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 4.750
4.875
5.000
5.125
5.250
0
10
20
30
40
50
60
70
80
ANALOG SUPPLY VOLTAGE (V)
fOUT (MHz)
_______________________________________________________________________________________
5
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
Typical Operating Characteristics (continued)
(AVCC = DVCC = 5V, external reference VREFIN = 1.196V, fCLK = 156.072MHz, RT = 27.4 referenced to AVCC, CL = 15pF, VOUT = 1VP-P, RSET = 3.83k, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 208.096MHz)
MAX5195 toc10
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 260.12MHz)
MAX5195 toc11
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 312.144MHz)
MAX5195 toc12
100 90 80 SFDR (dBc) 70 60 50 40 0 20 40 60 fOUT (MHz) 80 100 -18dBFS -6dBFS -12dBFS
100 90 80 SFDR (dBc) 70 60 50 40 -18dBFS
100 90 80 SFDR (dBc) 70 60 50 40 -18dBFS -6dBFS
-6dBFS -12dBFS
-12dBFS
120
0
20
40
60
80
100
120
140
0
20
40
60
80
100 120 140 160
fOUT (MHz)
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (fOUT = 16MHz AT -12dBFS)
MAX5195 toc13
SPECTRAL PLOT, SINGLE-TONE SFDR FOR A 10MHz WINDOW
MAX5195 toc14
SPECTRAL PLOT, SINGLE-TONE SFDR FOR A 10MHz WINDOW
-10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 -110 fCENTER fCLK = 260.12MHz fCENTER = 19.3975MHz OUTPUT AMPLITUDE: -12dBFS
MAX5195 toc15
83 82 81 SFDR (dBc) 80 79 78 77
fCLK = 160MHz
0 -10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 -110 fCENTER
0
fCLK = 156.072MHz fCENTER = 19.416 MHz OUTPUT AMPLITUDE: -12dBFS
-40
-15
10
35
60
85
10 12 14 16 18 20 22 24 26 28 OUTPUT FREQUENCY (MHz)
10 12 14 16 18 20 22 24 26 28 OUTPUT FREQUENCY (MHz)
TEMPERATURE (C)
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY (fOUT = 19MHz)
MAX5195 toc16
MULTITONE (4 TONES) POWER RATIO vs. CLOCK FREQUENCY
MAX5195 toc17
85 -6dBFS 81
-70 32MHz/-18dBFS
-75 4-TONE MTPR (dBc)
SFDR (dBc)
77
-12dBFS
-80
18MHz/-18dBFS 32MHz/-15dBFS
73
-85
69
-18dBFS
-90
18MHz/-15dBFS
65 150 180 210 240 fCLK (MHz) 270 300 330
-95 150 180 210 240 fCLK (MHz) 270 300 330
6
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC
Typical Operating Characteristics (continued)
(AVCC = DVCC = 5V, external reference VREFIN = 1.196V, fCLK = 156.072MHz, RT = 27.4 referenced to AVCC, CL = 15pF, VOUT = 1VP-P, RSET = 3.83k, TA = +25C, unless otherwise noted.)
MULTITONE (8 TONES) POWER RATIO vs. CLOCK FREQUENCY
MAX5195 toc18
MAX5195
OUTPUT RISE/FALL TIMES
MAX5195 toc19
-70.0 32MHz/-24dBFS -73.0 8-TONE MTPR (dBc) 18MHz/-24dBFS -76.0 32MHz/-21dBFS -79.0
90%
200mV/div 10%
-82.0
18MHz/-21dBFS
-85.0 150 180 210 240 fCLK (MHz) 270 300 330 1ns/div
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16, 47 17, 46 18 19 20 21 22 NAME D9P D8N D8P D7N D7P CLKP CLKN D6N D6P D5N D5P D4N D4P D3N D3P DVCC DGND D2N D2P D1N D1P D0N Data Bit 9 Complementary Data Bit 8 Data Bit 8 Complementary Data Bit 7 Data Bit 7 Converter Clock Input. Positive input terminal for LVPECL-compatible differential converter clock. Complementary Converter Clock Input. Negative input terminal for LVPECL-compatible differential converter clock. Complementary Data Bit 6 Data Bit 6 Complementary Data Bit 5 Data Bit 5 Complementary Data Bit 4 Data Bit 4 Complementary Data Bit 3 Data Bit 3 Digital Supply Voltage. Accepts a 4.75V to 5.25V supply voltage range. Bypass to DGND with a capacitor combination of 10F in parallel with 0.1F and 47pF. Digital Ground Complementary Data Bit 2 Data Bit 2 Complementary Data Bit 1 Data Bit 1 Complementary Data Bit 0 (LSB) FUNCTION
_______________________________________________________________________________________
7
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
Pin Description (continued)
PIN 23 24 25, 29, 32, 33, 35 26 27, 28 30 31 34 36 37 38 39 40 41 42 43 44 45 48 NAME D0P T.P. AVCC REFOUT AGND OUTN OUTP AMPOUT RSET REFIN D13N D13P D12N D12P D11N D11P D10N D10P D9N Data Bit 0 (LSB) Test Point. Must be connected to LVPECL high level (2.4V) for optimum dynamic performance. Analog Supply Voltage. Accepts a 4.75V to 5.25V supply voltage range. Bypass to AGND with a capacitor combination of 10F in parallel with 0.1F and 47pF. Reference Output. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F capacitor to AGND, if an external reference source is used. Analog Ground Complementary DAC Output. Negative terminal for differential voltage output. DAC Output. Positive terminal for differential voltage output. Control Amplifier Output. For stable operation, bypass to AGND with a combination of a 3k resistor in parallel with a 1.5F tantalum capacitor. Output Current Set Resistor. External resistor (3.83k to 7.66k) sets the full-scale current of the DAC. Reference Input. Accepts an input voltage range of 1.196V 8%. Bypass to AGND with a 0.1F capacitor, when used with the internal bandgap reference. Complementary Data Bit 13 (MSB) Data Bit 13 (MSB) Complementary Data Bit 12 Data Bit 12 Complementary Data Bit 11 Data Bit 11 Complementary Data Bit 10 Data Bit 10 Complementary Data Bit 9 FUNCTION
8
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC
Detailed Description
Architecture
The MAX5195 is a high-performance, 14-bit, segmented current-source array DAC (Figure 1) capable of operating with clock speeds up to 260MHz. The converter consists of separate input and DAC registers, followed by a current-source array. This current-source array is capable of generating differential full-scale currents in the range of 10mA to 20mA. An internal R2R resistor network, in combination with external 27.4 termination resistors, convert these differential output currents into a differential output voltage with a peak-to-peak output voltage range of 0.5V to 1V. An integrated 1.2V bandgap reference, control amplifier, and user-selectable, external resistor determine the data converter's full-scale output range.
Internal Reference and Control Amplifier
The MAX5195 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIN serves as the input for an external reference source, and REFOUT provides a 1.2V output voltage, if the internal reference is used. For internal reference operation, REFIN and REFOUT must be connected together and decoupled to AGND with a 1F capacitor in parallel with a 0.1F capacitor for stable operation. The MAX5195 reference circuit also employs a control amplifier, designed to regulate the full-scale current IFS for the differential current outputs of the MAX5195. For stable operation, the output AMPOUT of this amplifier must be bypassed with a 3k resistor in parallel with a 1.5F tantalum capacitor to AGND. Configured as a voltage-to-current amplifier, the output current can be calculated as follows: IFS = 64 IREF - 1LSB
MAX5195
DVCC
DGND
1.2V REFERENCE
BIAS
R2R NETWORK
AGND AVCC
REFOUT REFIN CURRENT-SOURCE ARRAY OUTP OUTN
RSET
CLKN CLKP
INPUT REGISTER
DECODER
INPUT LATCH
MAX5195
14 D0N/D0P-D13N/D13P
Figure 1. Simplified MAX5195 Block Diagram _______________________________________________________________________________________ 9
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
Table 1. IFS and RSET Selection Matrix Based on a Typical 1.2V Reference Voltage
FULL-SCALE CURRENT IFS (mA) 10 12 14 16 18 20 REFERENCE CURRENT IREF (A) 156.26 187.50 218.80 250.00 281.30 312.50 RSET (k) CALCULATED 7.68 6.40 5.49 4.80 4.27 3.84 1% EIA STD 7.50 6.34 5.49 4.75 4.22 3.83 OUTPUT VOLTAGE VOUTP/N* (mVP-P) 500 600 700 800 900 1000
*Terminated into a 27.4 load (see Analog Outputs section for details) referenced to AVCC.
1.5F MAX5195
3k AVCC
IFS = 64 IREF - (IFS / 214) where I REF is the reference output current (I REF = VREFOUT/RSET) and IFS is the full-scale current. RSET is the reference resistor that determines the amplifier's output current (Figure 2) on the MAX5195. See Table 1 for a matrix of different IFS and RSET selections.
1.2V REFERENCE REFOUT 0.1F 1F REFIN RSET IREF = VREFOUT/RSET IREF OUTP CURRENT-SOURCE ARRAY OUTN
External Reference Operation
Figure 3 illustrates a low-impedance reference source applied to the data converter for external reference operation. REFIN allows an input voltage range of 1.196V 8%. Use a fixed output voltage reference source such as the 1.2V, 25ppm/C (typ) MAX6520 bandgap reference for improved accuracy and drift performance. Bypass the unused REFOUT pin of the MAX5195 with a 1F capacitor to AGND.
NOTE: CONNECT REFIN AND REFOUT TOGETHER FOR INTERNAL REFERENCE OPERATION.
Figure 2. Internal Reference Configuration
1.5F
3k AVCC MAX5195
AMPOUT
1.2V REFERENCE REFOUT 1F REFIN
MAX6520
RSET IREF = VREFOUT/RSET IREF CURRENT-SOURCE ARRAY
OUTP OUTN
Figure 3. External Reference Configuration Using the MAX6520 10 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
Table 2. LVPECL Voltage Levels
PARAMETER Input Voltage High Input Voltage Low Common-Mode Level MINIMUM LVPECL SPECIFICATION VCC** - 1.16V VCC** - 1.81V VCC** - 1.3V MAXIMUM LVPECL SPECIFICATION VCC** - 0.88V VCC** - 1.48V
**VCC is the supply voltage associated with the LVPECL source. A typical VCC level associated with LVPECL is 3.3V, which sets the common-mode level to 2V, allowing a typical peak-to-peak signal swing of 0.8V.
LVPECL-Compatible Digital Inputs (D0P-D13P, D0N-D13N)
The MAX5195 digital interface consists of 14 differential, LVPECL-compatible digital input pins. These inputs follow standard positive binary coding where D0P and D0N represent the differential inputs to the least significant bit (LSB), and D13P and D13N represent the differential pair associated with the most significant bit (MSB). D0P/N through D13P/N accept LVPECL input levels of 0.8VP-P (Table 2). Each of the digital input terminals can be terminated with a separate 50 resistor; however, to achieve the lowest noise performance, it is recommended to terminate each differential pair with a 100 resistor located between the positive and negative input terminals.
provides for minimum setup and hold times (<2ns), allowing for noncritical external interface timing (Figure 4). For best AC performance, a differential, DC-coupled clock signal with LVPECL-compatible voltage levels (Table 2) should be used. The MAX5195 operates properly with a clock duty cycle set within the limits listed in the Electrical Characteristics table. However, a 50% duty cycle should be utilized for optimum dynamic performance. To maintain the DAC's excellent dynamic performance, clock and data signals should originate from separate signal sources.
Analog Outputs (OUTP, OUTN)
The MAX5195's current array is designed to drive fullscale currents of 10mA to 20mA into an internal R2R resistor network (RR2R). To achieve the desired differential output voltage range of 0.5VP-P to 1VP-P, both OUTP and OUTN should be externally terminated into 27.4 (RT), resulting in a combined load of RLOAD = 25 (Figure 5): RLOAD = RR2R || RT RLOAD = (285 27.4) / (285 + 27.4) RLOAD = 25
Clock Inputs (CLKP, CLKN) and Data Timing Relationship
The MAX5195 features differential, LVPECL-compatible clock inputs. Internal edge-triggered flip-flops latch the input word on the rising edge of the clock-input pair CLKP/CLKN. The DAC is updated with the data word on the next rising edge of the clock input. This results in a conversion latency of one clock cycle. The MAX5195
tCH CLKP CLKN tSETUP tCL
tHOLD D13-D0
OUTP tPD
90% POINT
MAX5195 OUTN 10% POINT
tRISE, tFALL
Figure 4. Input/Output Timing Information ______________________________________________________________________________________ 11
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
AVCC AVCC RR2R 285 RR2R 285 RT 27.4 RLOAD = 25 OUTN OUTP RT 27.4 AVCC RLOAD = 25
The proportional, differential output voltages can then be used to drive a wideband RF transformer or a fast, low-noise, low-distortion operational amplifier to convert the differential voltage into a single-ended output. The MAX5195 analog outputs can also be configured in single-ended mode. For more details on different output configurations, see the Applications Information section.
Applications Information
Differential Coupling Using a Wideband RF Transformer
A wideband RF transformer such as the TTWB1010 (1:1 turns ratio) from Coilcraft can be used to convert the MAX5195 differential output signal to a single-ended signal (Figure 6). As long as the generated output spectrum is within the passband of the transformer, a differentially coupled transformer provides the best distortion performance. Additionally, the transformer helps to reject noise and even-order harmonics, provides electrical isolation, and is capable of delivering more power to the load.
AMPOUT
AGND RLOAD IS THE COMBINED LOAD OF THE INTERNAL R2R RESISTOR NETWORK IN PARALLEL WITH THE EXTERNAL TERMINATION RESISTOR.
MAX5195
Figure 5. Simplified Output Architecture
With a full-scale current of 10mA (20mA), both outputs OUTP and OUTN achieve a 0.25V (0.5V) voltage swing each, resulting in a 0.5VP-P (1VP-P) differential output signal. For applications that require an even smaller output voltage swing, the termination resistor value RT can be as low as 0.
AVCC, DVCC
Single-Ended Unbuffered Output Configuration
Figure 7a shows an unbuffered single-ended output, which is suitable for applications requiring a unipolar voltage output. The nominal termination resistor load of 27.4 (referred to AVCC) results in a differential output
AVCC
RT 27.4 OUTP
VOUT, SINGLE ENDED
1:1 D0-D13
AGND
14
OUTN RT 27.4
TTWB1010 AGND WIDEBAND RF TRANSFORMER PERFORMS DIFFERENTIAL-TOSINGLE-ENDED CONVERSION.
MAX5195
AGND, DGND
AVCC
Figure 6. Differential Coupling Using a Wideband RF Transformer 12 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
AVCC, DVCC AVCC
RT 27.4 OUTP VOUTP
D0-D13
AGND
VOUT_ = IFS x RLOAD 14
OUTN RT 27.4 AGND
VOUTN
MAX5195
AGND, DGND
AVCC
RLOAD: RESISTOR COMBINATION OF INTERNAL R2R NETWORK AND EXTERNAL TERMINATION RESISTOR
Figure 7a. Single-Ended Unbuffered Output Configuration
AVCC, DVCC RLOOP
OUTP
CLOOP
D0-D13 VOUT
14
AGND
OUTN
MAX5195
AGND, DGND
AVCC
Figure 7b. Single-Ended Buffered Output Configuration
swing of 1VP-P (0.5VP-P single ended) when applying a full-scale current of 20mA. Alternatively, an external unity-gain amplifier can be used to buffer the outputs. This circuit works as an I-V amplifier (Figure 7b), in which OUTP is held at AVCC by the inverting terminal of the buffer amplifier. OUTN should then be connected to AVCC to provide a DCcurrent path for the current switched to OUTP. The
amplifier's maximum output swing and the MAX5195 full-scale current determine the value of RLOOP. An optional roll-off capacitor (CLOOP) in the feedback loop helps to ease dV/dt requirements at the input of the operational amplifier. It is recommended that the amplifier's power-supply rails be higher than the resistor's output reference voltage AVCC due to its positive and negative output swing around AVCC.
______________________________________________________________________________________
13
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
Grounding, Bypassing, and Power-Supply Considerations
Grounding and power-supply decoupling can strongly influence the performance of the MAX5195. Unwanted digital crosstalk can couple through the input, reference, power supply, and ground connections, thus affecting dynamic performance. Proper grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This reduces EMI and internal crosstalk, which can also affect the dynamic performance of the MAX5195. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should be run on lines directly above the ground plane. Since the MAX5195 has separate analog and digital ground buses (AGND and DGND, respectively), the PC board should have separate analog and digital ground sections with only one point connecting the two planes. Digital signals should run above the digital ground plane and analog signals above the analog ground plane. Digital signals should be kept as far away from sensitive analog inputs, reference input lines, and clock inputs. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The MAX5195 has two separate power-supply inputs for analog (AVCC) and digital (DVCC). Each AVCC input should be decoupled with parallel ceramic chip capacitors of 10F in parallel with 0.1F and 47pF with these capacitors as close to the supply pins as possible and their opposite ends with the shortest possible connection to the ground plane (Figure 8). The DV CC pins should also have separate 10F in parallel with 0.1F and 47pF capacitors adjacent to their respective pins. Try to minimize the analog and digital load capacitances for proper operation.
5V 10F 1.5F 3k 0.1F 47pF
AMPOUT
DGND
DVCC AVCC 5V 47pF AGND 0.1F 10F
1.2V REFERENCE REFOUT REFIN RSET 1F 3.83k 0.1F
BIAS
R2R NETWORK
27.4 AGND OUTP CURRENT-SOURCE ARRAY OUTN 27.4 AGND VOUT
AGND INPUT REGISTER CLKP
2.4V 1.6V 260MHz, LVPECL
DECODER MAX5195
2V CLKN INPUT LATCH
14 D0N/D0P-D13N/D13P
Figure 8. Decoupling and Bypassing Techniques for MAX5195--Typical Operating Circuit 14 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC
The power-supply voltages should also be decoupled at the point where they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a network can also improve performance. The analog and digital power-supply inputs AVCC and DVCC of the MAX5195 allow a 4.75V to 5.25V supply voltage range. Enhanced Thermal Dissipation QFN-EP Package The MAX5195 is packaged in a thermally enhanced 48pin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and a low thermal junction-case (jc) resistance of 2C/W. In this package, the data converter die is attached to an EP lead frame. The back of the lead frame is exposed at the package bottom surface (the PC board side of the package, Figure 9. This allows the package to be attached to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (5.5mm 5.5mm), guarantees proper attachment of the chip, and can also be used for heat-sinking purposes. Designing thermal vias* into the land area and implementing large ground planes in the PC board design further enhance the thermal conductivity between board and package. To remove heat from a 48-pin QFN-EP package effectively, an array of 3 3 (or *Connect the land pattern to internal or external copper planes.
48-LEAD QFN PACKAGE WITH EXPOSED PAD
greater) vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) is recommended. A smaller via array can be used as well, but results in an increased ja. Note that efficient thermal management for the MAX5195 is strongly dependent on PC board and circuit design, component placement, and installation; therefore, exact performance figures cannot be provided. For more information on proper design techniques and recommendations to enhance the thermal performance of parts such as the MAX5195, refer to Amkor Technology's website at www.amkor.com.
MAX5195
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
DIE
BONDING WIRE
EPOXY EXPOSED PAD COPPER TRACE, 1oz TOP LAYER GROUND PLANE AGND, DGND POWER PLANE COPPER TRACE, 1oz
PC BOARD
GROUND PLANE (AGND) 3 x 3 ARRAY OF THERMAL VIAS THERMAL LAND COPPER PLANE, 1oz
MAX5195
Figure 9. MAX5195 Exposed Paddle/PC Board Cross Section ______________________________________________________________________________________ 15
14-Bit, 260Msps High-Dynamic Performance DAC MAX5195
Offset Error The offset error is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is at midscale. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Glitch Energy Glitch impulses are caused by asymmetrical switching times in the DAC architecture, which generates undesired output transients. The amount of energy that appears at DAC's output is measured over time and is usually specified in the pV-s range. Spurious-Free Dynamic Range SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of the next largest distortion component. SFDR is measured in dBc, with respect to the carrier frequency amplitude. Multitone Power Ratio (MTPR) A series of equally spaced ones is applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either input tone to the worst 3rd-order (or higher) IMD products. Note that 2nd-order IMD products usually fall at frequencies, which can be easily removed by digital filtering. Therefore, they are not as critical as 3rd-order IMDs. The two-tone IMD performance of the MAX5195 was tested with the two individual input tone levels set to -9dBFS and -12dBFS.
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC's resolution (N bits): SNRdB = 6.02dB N + 1.76dB However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading. SNR is therefore computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.
Chip Information
TRANSISTOR COUNT: 15,000 PROCESS: SiGe
16
______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic Performance DAC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN 28, 32,44, 48L.EPS
MAX5195
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX5195

	To Download MAX5195 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .